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FIXUP: rockchip: rk3399: fix the incorrect bit during m0_init
authorXing Zheng <zhengxing@rock-chips.com>
Tue, 20 Dec 2016 12:44:41 +0000 (20:44 +0800)
committerXing Zheng <zhengxing@rock-chips.com>
Fri, 24 Feb 2017 12:07:44 +0000 (20:07 +0800)
commit175476f9e561704ab309c60cba531d95b1c0aa6b
treef63f0740a57f260550fc9a87c4caa6ff45afc846tree | snapshot
parentca9286c68a8fe408912fc1cd1b1e1789339ce135commit | diff
FIXUP: rockchip: rk3399: fix the incorrect bit during m0_init

We found that the DUT will be hanged if we don't set the bit_1 of the
PMUCRU_GATEDIS_CON0. But, from the TRM, there is weird that the bit_1
is set the clk_center1_gating_dis, not clk_pmum0_gating_dis. Is the
TRM incorrect? We need to check it with the IC team and re-clean the
commit message and explain it tomorrow.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
plat/rockchip/rk3399/drivers/pmu/m0_ctl.c diff | blob | history
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